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a
Dual RF PLL Frequency Synthesizers ADF4206/ADF4207/ADF4208
GENERAL DESCRIPTION
FEATURES ADF4206: 550 MHz/550 MHz ADF4207: 1.1 GHz/1.1 GHz ADF4208: 2.0 GHz/1.1 GHz 2.7 V to 5.5 V Power Supply Selectable Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems Selectable Charge Pump Currents On-Chip Oscillator Circuit Selectable Dual Modulus Prescaler RF2: 32/33 or 64/65 RF1: 32/33 or 64/65 3-Wire Serial Interface Power-Down Mode
The ADF4206 family of dual frequency synthesizers can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Each synthesizer consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dualmodulus prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. The on-chip oscillator circuitry allows the reference input to be derived from crystal oscillators. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizers are used with an external loop filter and VCOs (Voltage Controlled Oscillators).
APPLICATIONS Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Base Stations for Wireless Radio (GSM, PCS, DCS, Control of all the on-chip registers is via a simple 3-wire interface. CDMA, WCDMA) The devices operate with a power supply ranging from 2.7 V Wireless LANS to 5.5 V and can be powered down when not in use. Communications Test Equipment CATV Equipment FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2 VP1 VP2
N = BP + A 11-BIT RF2 B-COUNTER RF2INA RF2INB RF2 PRESCALER 6-BIT RF2 A-COUNTER
ADF4206/ADF4207/ADF4208
PHASE COMPARATOR CHARGE PUMP RF2 LOCK DETECT CPRF2
OSCIN OSCOUT
OSCILLATOR 14-BIT RF2 R-COUNTER OUTPUT MUX SDOUT 14-BIT RF1 R-COUNTER RF1 LOCK DETECT MUXOUT
CLOCK DATA LE
22-BIT DATA REGISTER
N = BP + A 11-BIT RF1 B-COUNTER RF1INA RF1INB RF1 PRESCALER 6-BIT RF1 A-COUNTER PHASE COMPARATOR
CHARGE PUMP
CPRF1
REV. 0
DGNDRF1
AGNDRF1
DGNDRF2
AGNDRF2
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
1=V =3 ADF4206/ADF4207/ADF4208-SPECIFICATIONS1 (Votherwise2noted,V dBm10%, 5 V to10%; .) V 1, V 2 V 1, V 2 6.0 V; AGND = DGND = AGND = DGND = 0 V; T = T to T unless referred 50
DD DD DD DD P P RF1 RF1 RF2 RF2 A MIN MAX
Parameter RF/IF CHARACTERISTICS (3 V) RF1 Input Frequency (RF1IN) ADF4206 ADF4207 ADF4208 RF Input Sensitivity IF Input Frequency (RF2IN) ADF4206 ADF4207/ADF4208 IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 RF CHARACTERISTICS (5 V) RF1 Input Frequency (RF1IN) ADF4206 ADF4207 ADF4208 RF Input Sensitivity IF Input Frequency (RF2IN) ADF4206 ADF4207/ADF4208 IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency5 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy ICP Three-State Leakage Current LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD1 VDD2 VP IDD (IDD1 + IDD2)6 ADF4206 ADF4207 ADF4208 IDD1 ADF4206 ADF4207 ADF4208 IDD2 ADF4206 ADF4207 ADF4208 IP (IP1 + IP2) Low-Power Sleep Mode
B Version
B Chips2
Unit
Test Conditions/Comments See Figure 2 for input circuit. Use a square wave for frequencies lower than fMIN.
0.05/0.55 0.08/1.1 0.08/2.0 -15/+4 0.05/0.55 0.08/1.1 -15/+4 165
0.05/0.55 0.08/1.1 0.08/2.0 -15/+4 0.05/0.55 0.08/1.1 -15/+4 165
GHz min/max GHz min/max GHz min/max dBm min/max GHz min/max GHz min/max dBm min/max MHz max
Use a square wave for frequencies lower than fMIN. 0.05/0.55 0.08/1.1 0.08/2.0 -10/+4 0.05/0.55 0.08/1.1 -10/+4 200 0.05/0.55 0.08/1.1 0.08/2.0 -10/+4 0.05/0.55 0.08/1.1 -10/+4 200 GHz min/max GHz min/max GHz min/max dBm min/max MHz min/max GHz min/max GHz min/max dBm min/max MHz max
5/40 -2 10 100 55
5/40 -2 10 100 55
MHz min/max dBm min pF max A max MHz max
For f < 5 MHz Use Square Wave 0 to VDD AC-Coupled. When DC-Coupled, 0 to VDD Max (CMOS-Compatible)
5 1.25 2.5 1 0.8 x VDD 0.2 x VDD 1 10 VDD - 0.4 0.4 2.7/5.5 VDD1 VDD1/6.0 14 16.5 21 8 9 14 7.5 8.5 9 1 0.5
5 1.25 2.5 1 0.8 x VDD 0.2 x VDD 1 10 VDD - 0.4 0.4 2.7/5.5 VDD1 VDD1/6.0 14 16.5 21 8 9 14 7.5 8.5 9 1 0.5
mA typ mA typ % typ nA typ V min V max A max pF max V min V max V min/V max V min/V max mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max A typ VDD1, VDD2 VP1, VP2 6.0 V IOH = 500 A IOL = 500 A
9.5 mA Typical at VDD = 3 V, TA = 25C 11 mA Typical at VDD = 3 V, TA = 25C 14 mA Typical at VDD = 3 V, TA = 25C 5.5 mA Typical at VDD = 3 V, TA = 25C 6 mA Typical at VDD = 3 V, TA = 25C 9 mA Typical at VDD = 3 V, TA = 25C 5 mA Typical at VDD = 3 V, TA = 25C 5.5 mA Typical at VDD = 3 V, TA = 25C 5.5 mA Typical at VDD = 3 V, TA = 25C TA = 25C
-2-
REV. 0
ADF4206/ADF4207/ADF4208
Parameter NOISE CHARACTERISTICS Phase Noise Floor (RF1)7 ADF4206 ADF4207 ADF4208 ADF4206 ADF4207 ADF4208 Phase Noise Performance8 ADF4206 (RF1, RF2) ADF4207 (RF1, RF2) ADF4207 (RF1, RF2)9 ADF4208 (RF1) ADF4208 (RF1) ADF4208 (RF1)10 ADF4208 (RF2) Spurious Signals RF1, RF2 (20 kHz Loop B/W) RF1, RF2 (1 kHz Loop B/W) B Version B Chips2 Unit Test Conditions/Comments
-169 -171 -173 -160 -162 -164 -92 -90 -81 -85 -91 -66 -89 -80/-84 -65/-73
-169 -171 -173 -160 -162 -164 -92 -90 -81 -85 -91 -66 -89 -80/-84 -65/-73
dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dB typ dB typ
@ 25 kHz PFD Frequency @ 25 kHz PFD Frequency @ 25 kHz PFD Frequency @ 200 kHz PFD Frequency @ 200 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output @ 540 MHz Output, 200 kHz at PFD @ 900 MHz Output, 200 kHz at PFD @ 836 MHz, 30 kHz at PFD @ 1750 MHz Output, 200 kHz at PFD @ 900 MHz Output, 200 kHz at PFD @ 1750 MHz Output, 200 kHz at PFD @ 900 MHz Output, 200 kHz at PFD @ 200 kHz/400 kHz and 200 kHz PFD @10 kHz/20 kHz and 10 kHz PFD
NOTES 1 Operating temperature range is as follows: B Version: -40C to +85C. 2 The B Chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels. 5 Guaranteed by design. Sample tested to ensure compliance. 6 Typical values apply for VDD = 3 V; P = 32; RF1IN1/RF2IN2 for ADF4206 = 540 MHz; RF1 IN1/RF2IN2 for ADF4207 = 900 MHz; RF1 IN1/RF2IN2 for ADF4208 = 900 MHz. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 8 The phase noise is measured at a 1 kHz unless otherwise noted. The phase noise is measured with the EVAL-ADF4206/ADF4207EB or the EVAL-AD4208EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f REFOUT = 10 MHz @ 0 dBm). 9 fREFIN = 10 MHz; fPFD = 30 kHz; Offset Frequency = 300 Hz; f RF/IF = 836 MHz; N = 27866; Loop B/W = 3 kHz. 10 fREFIN = 10 MHz; fPFD = 10 kHz; Offset Frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz. Specifications subject to change without notice.
REV. 0
-3-
ADF4206/ADF4207/ADF4208 (V 1 = V 2 = 3 V 10%, 5 V TIMING CHARACTERISTICS AGND = DGND = 0 V; T = T
DD DD RF2 RF2 A
MIN
10%; VDD1, VDD2 VP1, VP2 6.0 V; AGNDRF1 = DGNDRF1 = to TMAX unless otherwise noted, dBm referred to 50 .)
Parameter t1 t2 t3 t4 t5 t6
Limit at TMIN to TMAX (B Version) 10 10 25 25 10 20
Unit ns min ns min ns min ns min ns min ns min
Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth
NOTES Guaranteed by design but not production tested. Specification subject to change without notice.
t3
CLOCK
t4
t1
DATA DB21 (MSB) DB20
t2
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C unless otherwise noted.)
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . -0.3 V to DVDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . -0.3 V to VP + 0.3 V OSCIN, OSCOUT, RF1IN (A, B), RF2IN (A, B) to GND . . . . . . . . . . . . -0.3 V to VDD + 0.3 V RFINA to RFINB (RF1, RF2) . . . . . . . . . . . . . . . . . . 320 mV Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4C/W
CSP JA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122C/W CSP JA (Paddle Not Soldered) . . . . . . . . . . . . . . . . 216C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high-performance RF integrated circuit with an ESD rating of < 2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDE
Model ADF4206BRU ADF4207BRU ADF4208BRU
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP)
Package Option* RU-16 RU-16 RU-20
*Contact the factory for chip availability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4206/ADF4207/ADF4208 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. 0
ADF4206/ADF4207/ADF4208
PIN FUNCTION DESCRIPTIONS
Pin No. 1
Mnemonic ADF4206/ ADF4207 ADF4208 VDD1 VDD1
Function Positive Power Supply for the RF1 Section. A 0.1 F capacitor should be connected between this pin and the RF1 ground pin, DGNDRF1. VDD1 should have a value of between 2.7 V and 5.5 V. VDD1 must have the same potential as VDD2. Power Supply for the RF1 Charge Pump. This should be greater than or equal to VDD. Output from the RF1 Charge Pump. This is normally connected to a loop filter which, in turn, drives the input to an external VCO. Ground Pin for the RF1 Digital Circuitry. Input to the RF1 Prescaler. This low-level input signal is normally taken from the RF1 VCO. Complementary Input to the RF1 Prescaler of the ADF4208. This point should be decoupled to the ground plane with a small bypass capacitor. Ground Pin for the RF1 Analog Circuitry. Oscillator Input. It has a VDD/2 threshold and can be driven from an external CMOS or TTL logic gate. Oscillator Output. This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled Reference Frequency to be accessed externally. See Table V. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Ground Pin for the RF2 Analog Circuitry. Complementary Input to the RF2 Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor. Input to the RF2 Prescaler. This low-level input signal is normally ac-coupled to the external VCO. Ground Pin for the RF2, Digital, Interface, and Control Circuitry. Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives the input to an external VCO. Power Supply for the RF2 Charge Pump. This should be greater than or equal to VDD. Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 F capacitor should be connected between this pin and the RF2 ground Pin, DGNDRF2. VDD2 should have a value between 2.7 V and 5.5 V. VDD2 must have the same potential as VDD1.
PIN CONFIGURATIONS
2 3 4 5 6 7 8 9 10 11
V P1 CPRF1 DGNDRF1 RF1IN OSCIN OSCOUT MUXOUT CLK DATA LE
VP1 CPRF1 DGNDRF1 RF1INA RFINB AGNDRF1 OSCIN OSCOUT MUXOUT CLK
12 13 14 15 16 17 18 19 20
RF2IN DGNDRF2 CPRF2 V P2 VDD2
DATA LE AGNDRF2 RF2INB RF2INA DGNDRF2 CPRF2 VP2 VDD2
TSSOP
VDD1 1 VP1 2 CPRF1 3 DGNDRF1
4 16 V 2 DD
TSSOP
VDD1 1 VP1 2 CPRF1 3 DGNDRF1 4 RF1IN A 5 RF1IN B 6 AGNDRF1 7 OSCIN 8 OSCOUT 9 MUXOUT 10
20 19 18
VDD2 VP2 CPRF2 DGNDRF2 RF2IN A RF2IN B
ADF4206/ ADF4207
15 V 2 P 14 CP RF2 13 DGND RF2 12 RF2 IN
ADF4208
17 16 15
RF1IN 5 OSCIN 6
TOP VIEW 11 LE (Not to Scale) 10 DATA OSCOUT 7 MUXOUT 8
9
CLK
TOP VIEW 14 AGNDRF2 (Not to Scale) 13 LE
12 11
DATA CLK
REV. 0
-5-
ADF4206/ADF4207/ADF4208 -Typical Performance Characteristics
0
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD GHz S MA R IMPEDANCE - OHMS 50
-10 -20
OUTPUT POWER - dB
FREQ 0.0 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 1.25
MAGS11 0.957111193 0.963546793 0.953621785 0.953757706 0.929831379 0.908459709 0.897303634 0.876862863 0.849338092 0.858403269 0.841888714 0.840354983 0.822165839
ANGS11 -3.130429321 -6.686426265 -11.19913586 -15.35637483 -20.3793432 -22.69144845 -27.07001443 -31.32240763 -33.68058163 -38.57674885 -41.48606772 -45.97597958 -49.19163116
FREQ 1.35 1.45 1.55 1.65 1.75 1.85 1.95 2.05 2.15 2.25 2.35 2.45 2.55
MAGS11 0.816886959 0.825983016 0.791737125 0.770543186 0.793897072 0.745765233 0.7517547 0.745594889 0.713387801 0.711578577 0.698487131 0.669871818 0.668353367
ANGS11 -51.80711782 -56.20373378 -61.21554647 -61.88187496 -65.39516615 -69.24884474 -71.21608147 -75.93169947 -78.8391674 -81.71934806 -85.49067481 -88.41958754 -91.70921678
REFERENCE LEVEL = -4.2dBm
-30 -40 -50 -60 -70 -80 -90
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 30
-90.2dBc/Hz
-100 -400k
-200k
900M 200k FREQUENCY - Hz
400k
TPC 1. S-Parameter Data for the AD4208 RF1 Input (Up to 2.5 GHz)
TPC 4. ADF4208 RF1 Reference Spurs (900 MHz, 200 kHz, 20 kHz)
0 -5
RF INPUT POWER - dBm
VDD = 5V VP = 5V
-40 -50 -60
PHASE NOISE - dBc/Hz
10dB/DIVISION RL = -40dBc/Hz rms NOISE = 0.52
-10 -15 -20 -25 TA = -40 C -30 TA = +25 C -35 0 0.5 1.0 1.5 2.0 2.5 RF INPUT SENSITIVITY - GHz 3.0 3.5 TA = +85 C
-70 -80 -90 -100 -110 -120 -130 -140 100Hz 0.52 rms
1kHz 10kHz 100kHz FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
TPC 2. Input Sensitivity for the ADF4208 (RF1)
TPC 5. ADF4208 RF1 Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz)
0 -10 -20
OUTPUT POWER - dB
REFERENCE LEVEL = -4.2dBm
-30 -40 -50 -60 -70 -80 -90
PHASE NOISE - dBc/Hz
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 19
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0.62 rms 10dB/DIVISION RL = -40dBc/Hz rms NOISE = 0.62
-90.5dBc/Hz
-100
-2k
-1k
900M FREQUENCY - Hz
1k
2k
-140 100Hz
1kHz 10kHz 100kHz FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
TPC 3. ADF4208 RF1 Phase Noise (900 MHz, 200 kHz, 20 kHz)
TPC 6. ADF4208 RF1 Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz)
-6-
REV. 0
ADF4206/ADF4207/ADF4208
0 -10 -20
OUTPUT POWER - dB
REFERENCE LEVEL = -4.2dBm
-30 -40 -50 -60 -70 -80 -90
OUTPUT POWER - dB
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 35kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 30
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -79.6dBc REFERENCE LEVEL = -5.7dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 3kHz RES. BANDWIDTH = 3Hz VIDEO BANDWIDTH = 3Hz SWEEP = 255 SECONDS POSITIVE PEAK DETECT MODE
-89.3dBc
-100 -400k -200k 200k 900M FREQUENCY - Hz 400k
-400k
-200k
1750M 40k FREQUENCY - Hz
80k
TPC 7. ADF4208 RF1 Reference Spurs (900 MHz, 200 kHz, 35 kHz)
TPC 10. ADF4208 RF1 Reference Spurs (1750 MHz, 30 kHz, 3 kHz)
0 -10 -20 REFERENCE LEVEL = -8.0dBm
-120
OUTPUT POWER - dB
-30 -40 -50 -60 -70 -80 -90
PHASE NOISE - dBc/Hz
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 3kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 477ms AVERAGES = 10
VDD = 3V VP = 5V -130
-140 ADF4206 -150 ADF4207 ADF4208 -170
-160
-75.2dBc/Hz
-100 -400
-180
-200
1750M 200 FREQUENCY - Hz
400
1
10 100 1000 PHASE DETECTOR FREQUENCY - kHz
10000
TPC 8. ADF4208 RF1 Phase Noise (1750 MHz, 30 kHz, 3 kHz)
TPC 11. ADF4208 RF1 Phase Noise vs. PFD Frequency
-40 -50 -60
PHASE NOISE - dBc/Hz
-60
10dB/DIVISION RL = -40dBc/Hz
PHASE NOISE - dBc/Hz
-70
VDD = 3V VP = 3V
-70 -80 -90 -100 -110 -120 -130 -140 100Hz 1.6 rms
-80
-90
1kHz 10kHz 100kHz FREQUENCY OFFSET FROM 1750MHz CARRIER
1MHz
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 9. ADF4208 RF1 Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz)
TPC 12. ADF4208 RF1 Phase Noise vs. Temperature (900 MHz, 200 kHz, 20 kHz)
REV. 0
-7-
ADF4206/ADF4207/ADF4208
-60 VDD = 3V VP = 5V -70 2.0 3.0 VDD = 3V VP = 3V
FIRST REFERENCE SPUR - dBc
2.5
DIDD - mA
-80
1.5
1.0 -90 0.5
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
0
0
50 100 150 PRESCALER OUTPUT FREQUENCY - MHz
200
TPC 13. ADF4208 RF1 Reference Spurs vs. Temperature (900 MHz, 200 kHz, 20 kHz)
TPC 16 DIDD vs. Prescaler Output Frequency (All Models, RF1 and RF2)
-5 -15
FIRST REFERENCE SPUR - dBc
10 VDD = 3V VP = 5V 9 8 7
AIDD - mA
ADF4208
-25 -35 -45 -55 -65 -75 -85 -95 -105 0 1 2 3 TUNING VOLTAGE - V
6 5 4 3 2 1 0 ADF4206 ADF4207
4
5
32/33 PRESCALER VALUE
64/65
TPC 14. ADF4208 RF1 Reference Spurs vs. VTUNE (900 MHz, 200 kHz, 20 kHz)
TPC 17. ADF4206/ADF4207/ADF4208 AIDD vs. Prescaler Value (RFI)
-120 VDD = 3V VP = 5V -130
PHASE NOISE - dBc/Hz
-140 ADF4206 -150
-160 ADF4207 ADF4208 -170
-180 1 10 100 1000 PHASE DETECTOR FREQUENCY - kHz 10000
TPC 15. ADF4208 RF2 Phase Noise vs. PFD Frequency
-8-
REV. 0
ADF4206/ADF4207/ADF4208
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION A AND B COUNTERS
The reference input stage is shown in Figure 2. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. Typical recommended external components are shown in Figure 2.
POWER-DOWN CONTROL
The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The devices are guaranteed to work when the prescaler output is 200 MHz or less.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: fVCO = [(P x B) + A] x fREFIN/R fVCO = Output frequency of external voltage controlled oscillator (VCO). P = Preset modulus of dual modulus prescaler (32/33, 64/65). = Preset Divide Ratio of binary 11-bit counter (1 to 2047). = Preset Divide Ratio of binary 6-bit A counter (0 to 63).
NC OSCIN NC 30pF SW1
100k SW2 BUFFER SW3 TO R COUNTER
30pF OSCOUT 18k
NO
B A
Figure 2. RF Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 3. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler.
BIAS GENERATOR 2k 1.6V AVDD 2k
fREFIN = Output frequency of the external reference frequency oscillator. R = Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
RFINA
RFINB
N = BP + A 11-BIT B COUNTER LOAD
AGND
TO PFD
FROM RF INPUT STAGE
PRESCALER P/P + 1 MODULUS CONTROL N DIVIDER
LOAD 6-BIT A COUNTER
Figure 3. RF Input Stage
PRESCALER
The dual modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). This prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. It is based on a synchronous 4/5 core. The prescaler is selectable. Both RF1 and RF2 can be set to either 32/33 or 64/65. DB20 of the AB counter latch selects the value. See Tables IV and VI.
Figure 4. A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic.
REV. 0
-9-
ADF4206/ADF4207/ADF4208
VP CHARGE PUMP HI D1 U1 R DIVIDER CLR1 Q1 UP
RF2 ANALOG LOCK DETECT RF2 R COUNTER OUTPUT RF2 N COUNTER OUTPUT RF2/RF1 ANALOG LOCK DETECT RF1 R COUNTER OUTPUT RF1 N COUNTER OUTPUT RF1 ANALOG LOCK DETECT DVDD
MUX
CONTROL
MUXOUT
DELAY ELEMENT
U3
CP
DGND
Figure 6. MUXOUT Circuit
CLR2 HI D2 U2 N DIVIDER CPGND Q2
Lock Detect
DOWN
MUXOUT can be programmed for analog lock detect. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. When lock has been detected it is high with narrow low-going pulses.
INPUT SHIFT REGISTER
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 5. PFD Simplified Schematic and Timing (In Lock)
The PFD includes a delay element which sets the width of the antibacklash phase. The typical value for this is in the ADF4206 family is 3 ns. The pulse ensures that there is no deadzone in the PFD transfer function and minimizes phase noise and reference spurs.
MUXOUT AND LOCK DETECT
The functional block diagram for the ADF4206 family is shown on Page 1. The main blocks include a 22-bit input shift register, a 14-bit R counter, and an 17-bit N counter, comprising a 6-bit A counter and an 11-bit B counter. Data is clocked into the 22-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs DB1, DB0, as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table I.
Table I. C2, C1 Truth Table
Control Bits C2 C1 0 0 1 1 0 1 0 1
Data Latch RF2 R Counter RF2 AB Counter (and Prescaler Select) RF1 R Counter RF1 AB Counter (and Prescaler Select)
The output multiplexer on the ADF4206 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11, and P12. See Tables III and V. Figure 6 shows the MUXOUT section in block diagram form.
-10-
REV. 0
ADF4206/ADF4207/ADF4208
Table II. ADF4206 Family Latch Summary
RF2 REFERENCE COUNTER LATCH
THREE-STATE CPRF2 RF2 PD POLARITY RF2 LOCK DETECT RF2 CP GAIN RF2 FO NOT USED
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P4 P3 P2 P5 P1 R14 R13
DB13 DB12 R12 R11
DB11 DB10 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
RF2 AB COUNTER LATCH
RF2 POWER-DOWN RF2 PRESCALER NOT USED
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P7 P6 B11 B10 B9 B8 B7 B6
DB13 DB12 B5 B4
DB11 DB10 B3 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (0)
DB0 C1 (0)
RF1 REFERENCE COUNTER LATCH
THREE-STATE CPRF1 RF1 PD POLARITY RF1 LOCK DETECT RF1 CP GAIN RF1 FO NOT USED
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P12 P11 P10 P13 P9 R14 R13
DB13 DB12 R12 R11
DB11 DB10 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (1)
DB0 C1 (0)
RF1 AB COUNTER LATCH
RF1 POWER-DOWN RF1 PRESCALER NOT USED
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P16 P14 B11 B10 B9 B8 B7 B6
DB13 DB12 B5 B4
DB11 DB10 B3 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (1)
DB0 C1 (1)
REV. 0
-11-
ADF4206/ADF4207/ADF4208
Table III. RF2 Reference Counter Latch Map
RF2 REFERENCE COUNTER LATCH
THREE-STATE CPRF2 RF2 LOCK DETECT RF2 PD POLARITY RF2 CP GAIN RF2 FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 P4 P3 P2 P5 P1 R14
DB14 R13
DB13 DB12 R12 R11
DB11 DB10 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
R12 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383
P1 0 1
PD POLARITY NEGATIVE POSITIVE
P5 0 1
ICP 1.25 mA 4.375 mA
P2 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 P11 FROM RF1 R LATCH 0 0 0 0 0 X 0 X 0 1 0 1 1 X 1 X 1 0 1 1 1 0 1 1
P4 0 0 1 1 0 0 0 0 1 1 1 1
P3 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE RF2 ANALOG LOCK DETECT RF2 REFERENCE DIVIDER OUTPUT RF2 N DIVIDER OUTPUT RF1 ANALOG LOCK DETECT RF1/RF2 ANALOG LOCK DETECT RF1 REFERENCE DIVIDER RF1 N DIVIDER FAST LOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT RF2 COUNTER RESET RF1 COUNTER RESET RF2 AND RF1 COUNTER RESET
-12-
REV. 0
ADF4206/ADF4207/ADF4208
Table IV. RF2 AB Counter Latch Map
RF2 AB COUNTER LATCH
RF2 POWERDOWN RF2 PRESCALER
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P7 P6 B11 B10 B9 B8 B7 B6
DB13 DB12 B5 B4
DB11 DB10 B3 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (0)
DB0 C1 (1)
A6 X X X X . . . X X
A5 X X X X . . . X X
A4 0 0 0 0 . . . 1 1
A3 0 0 0 0 . . . 1 1
A2 0 0 1 1 . . . 1 1
A1 0 1 0 1 . . . 0 1
A COUNTER DIVIDE RATIO 0 1 2 3
14 15
B11 0 0 0 0 . . . 1 1 1 1
B10 0 0 0 0 . . . 1 1 1 1
B9 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 0 . . . 1 1 1 1
B2 0 0 1 1 . . . 0 0 1 1
B1 0 1 0 1 . . . 0 1 0 1
B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 2044 2045 2046 2047
P6 0 1
RF2 PRESCALER 64/65 32/33
P7 0 1
RF2 SECTION NORMAL OPERATION POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES OF Nx FREF, NMIN IS (P2 - P).
REV. 0
-13-
ADF4206/ADF4207/ADF4208
Table V. RF1 Reference Counter Latch Map
RF1 REFERENCE COUNTER LATCH
RF1 LOCK DETECT THREE-STATE CPRF1 RF1 PD POLARITY RF1 CP GAIN RF1 FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P12 P11 P10 P13 P9 R14 R13
DB13 DB12 R12 R11
DB11 DB10 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (1)
DB0 C1 (0)
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
R12 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383
P9 0 1
PD POLARITY NEGATIVE POSITIVE
P13 0 1
ICP 1.25 mA 4.375 mA
P10 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 0 0 0 0 0 0 1 1 1 1 1 1
P11 0 0 X X 1 1 X X 0 0 1 1
P4 P3 FROM RF2 R LATCH 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 1 1 0 1 1 1 1 0 1
MUXOUT LOGIC LOW STATE RF2 ANALOG LOCK DETECT RF2 REFERENCE DIVIDER OUTPUT RF2 N DIVIDER OUTPUT RF1 ANALOG LOCK DETECT RF1/RF2 ANALOG LOCK DETECT RF1 REFERENCE DIVIDER RF1 N DIVIDER FAST LOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT RF2 COUNTER RESET RF1 COUNTER RESET RF2 AND RF1 COUNTER RESET
-14-
REV. 0
ADF4206/ADF4207/ADF4208
Table VI. RF1 AB Counter Latch Map
RF1 AB COUNTER LATCH
RF1 POWERDOWN RF1 PRESCALER
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 P16 P14 B11 B10 B9 B8 B7
DB14 DB13 B6 B5
DB12 DB11 DB10 B4 B3 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (1)
DB0 C1 (1)
A6 0 0 0 0 . . . 1 1
A5 0 0 0 0 . . . 1 1
A4 0 0 0 0 . . . 1 1
A3 0 0 0 0 . . . 1 1
A2 0 0 1 1 . . . 1 1
A1 0 1 0 1 . . . 0 1
A COUNTER DIVIDE RATIO 0 1 2 3
62 63
B11 0 0 0 0 . . . 1 1 1 1
B10 0 0 0 0 . . . 1 1 1 1
B9 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 1 . . . 1 1 1 1
B2 0 1 1 0 . . . 0 0 1 1
B1 1 0 1 0 . . . 0 1 0 1
B COUNTER DIVIDE RATIO 1 2 3 3 . . . 2044 2045 2046 2047
P14 0 1
RF1 PRESCALER 64/65 32/33
P16 0 1
RF1 SECTION NORMAL OPERATION POWER-DOWN N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF N, NMIN IS (P2 - P).
REV. 0
-15-
ADF4206/ADF4207/ADF4208
PROGRAM MODES Asynchronous RF1 Power-Down
Table III and Table V show how to set up the Program Modes in the ADF420x family. The following should be noted: 1. RF2 and RF1 Analog Lock Detect indicate when the PLL is in lock. When the loop is locked and either RF2 or RF1 Analog Lock Detect is selected, the MUXOUT pin will show a logic high with narrow low-going pulses. When the RF2/RF1 Analog Lock Detect is chosen, the locked condition is indicated only when both RF2 and RF1 loops are locked. 2. The RF2 Counter Reset mode resets the R and AB counters in the RF2 section and also puts the RF2 charge pump into three-state. The RF1 Counter Reset mode resets the R and AB counters in the RF1 section and also puts the RF1 charge pump into three-state. The RF2 and RF1 Counter Reset mode does both of the above. Upon removal of the reset bits, the AB counter resumes counting in close alignment with the R counter (maximum error is one prescaler output cycle). 3. The Fastlock mode uses MUXOUT to switch a second loop filter damping resistor to ground during Fastlock operation. Activation of Fastlock occurs whenever RF1 CP Gain in the RF1 Reference counter is set to one.
POWER-DOWN
If P10 of the ADF420x family has been set to "1" (three-state the RF1 charge pump), and P16 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the RF1 power-down bit (P16). Activation of either synchronous or asynchronous power-down forces the RF2/RF1 loop's R and N dividers to their load state conditions and the RF2/RF1 input section is debiased to a high impedance state. The reference oscillator circuit is only disabled if both the RF2 and RF1 power-downs are set. The input register and latches remain active and are capable of loading and latching data during all the power-down modes. The RF2/RF1 section of the devices will return to normal powered up operation immediately upon LE latching a "0" to the appropriate power-down bit.
IF SECTION (RF2) Programmable RF2 Reference (R) Counter
If control bits (C2, C1) are (0, 0), the data is transferred from the input shift register to the 14-bit RF2 R counter. Table III shows the input shift register data format for the RF2 R counter and the divide ratios possible.
RF2 Phase Detector Polarity
It is possible to program the ADF420x family for either synchronous or asynchronous power-down on either the RF2 or RF1 side.
Synchronous RF2 Power-Down
P1 sets the RF2 Phase Detector Polarity. When the RF2 VCO characteristics are positive, this should be set to "1." When they are negative, it should be set to "0." See Table III.
RF2 Charge Pump Three-State
Programming a "1" to P7 of the ADF420x family will initiate a power-down. If P2 of the ADF420x family has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into threestate and then complete the power-down.
Asynchronous RF2 Power-Down
P2 puts the RF2 charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table III.
RF2 Program Modes
If P2 of the ADF420x family has been set to "1" (three-state the RF2 charge pump), and P7 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the RF2 power-down bit (P7).
Synchronous RF1 Power-Down
Table III and Table V show how to set up the Program Modes in the ADF420x family.
RF2 Charge Pump Currents
Bit P5 programs the current setting for the RF2 charge pump. See Table III.
Programmable RF2 AB Counter
Programming a "1" to P16 of the ADF420x family will initiate a power-down. If P10 of the ADF420x family has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into threestate and then complete the power-down.
If control bits (C2, C1) are (0, 1), the data in the input register is used to program the RF2 AB counter. The AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter). Table IV shows the input register data format for programming the RF2 AB counter and the divide ratios possible.
RF2 Prescaler Value
P6 in the RF2 AB counter latch sets the RF2 prescaler value. See Table IV.
RF2 Power-Down
P7 in Table IV is the power-down bit for the RF2 side.
-16-
REV. 0
ADF4206/ADF4207/ADF4208
RF SECTION (RF1) Programmable RF1 Reference (R) Counter Programmable RF1 AB Counter
If control bits (C2, C1) are (1, 0), the data is transferred from the input shift register to the 14 Bit RF1 R counter. Table V shows the input shift register data format for the RF1 R counter and the divide ratios possible.
RF1 Phase Detector Polarity
If control bits (C2, C1) are (1, 1), then the data in the input register is used to program the RF1 AB counter. The AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter). Table VI shows the input register data format for programming the RF1 AB counter and the divide ratios possible. See Table VI.
RF1 Prescaler Value
P9 sets the RF1 Phase Detector Polarity. When the RF1 VCO characteristics are positive this should be set to "1." When they are negative it should be set to "0." See Table V.
RF1 Charge Pump Three-State
P14 in the RF1 A, B counter latch set the RF1 prescaler value. See Table VI.
RF1 Power-Down
P10 puts the RF1 charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table V.
RF1 Program Modes
Setting P16 in the RF1 AB counter high powers down RF1 side.
RF Fastlock
Table III and Table V show how to set up the Program Modes in the ADF420x family.
RF1 Charge Pump Currents
Replaced with a P13 programs the current setting for the RF1 charge pump. See Table V.
The fastlock feature can improve the lock time of the PLL. It increases charge pump current to a maximum for a period of time. Fastlock of the ADF420x family is activated by setting P13 in the reference counter high and setting the fastlock switch on using MUXOUT. Switching in an external resistor using MUXOUT compensates the loop dynamics for the effect of increasing charge pump current. Setting P13 low removes the PLL from fastlock mode.
IFOUT
VP
VDD
VP
RFOUT
100pF 18 18 18
VCC 100pF VCO190-125T 3.3k 2.7k 1.3nF 13nF 620pF VP2 CPRF2 VDD2 VDD1 VP1 CPRF1
VCC
100pF 18
VCO190-1068U 100pF 18
18
ADF4207
100pF RF2IN
MUXOUT RF1IN
LOCK DETECT
100pF 51
AGNDRF1
51 30pF 30pF 10MHz 18k
OSCIN OSCOUT
DGNDRF1
DGNDRF2
AGNDRF2
DECOUPLING CAPACITORS (22 F/10pF) ON VDD, VP OF THE ADF4207, AND ON VCC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4207
REV. 0
-17-
SPI-COMPATIBLE SERIAL BUS
CLK DATA LE
ADF4206/ADF4207/ADF4208
APPLICATIONS SECTION Local Oscillator for GSM Handset Receiver
Figure 7 shows the ADF4207 being used in a classic superheterodyne receiver to provide the required LOs (Local Oscillators). In this circuit, the reference input signal is applied to the circuit at OSCIN and is being generated by a 10 MHz Crystal Oscillator. This is a low-cost solution and for better performance over temperature, a TCXO (Temperature Controlled Crystal Oscillator) may be used instead. In order to have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 50, using the on-chip reference counter. The RF output frequency range is 1050 MHz to 1086 MHz. Loop filter component values are chosen so that the loop bandwidth is 20 kHz. The synthesizer is set up for a charge pump current of 4.375 mA and the VCO sensitivity is 15.6 MHz/V.
The IF output is fixed at 125 MHz. The IF loop bandwidth is chosen to be 20 kHz with a channel spacing of 200 kHz. Loop filter component values are chosen accordingly.
Local Oscillator for WCDMA Receiver
Figure 8 shows the ADF4208 being used to generate the local oscillator frequencies for a Wideband CDMA (WCDMA) system. The RF output range needed is 1720 MHz to 1780 MHz. The VCO190-1750T will accomplish this. Channel spacing is 200 kHz with a 20 kHz loop bandwidth. VCO sensitivity is 32 MHz/V. Charge pump current of 4.375 mA is used and the desired phase margin for the loop is 45. The IF output is fixed at 200 MHz. The VCO190-200T is used. It has a sensitivity of 10 MHz/V. Channel spacing and loop bandwidth is chosen to be the same as the RF side.
IFOUT
VP
VDD
VP
RFOUT
100pF 18 18 18
VCC 100pF VCO190-200T 3.3k 2.7k 1.3nF 13nF 620pF VP2 CPRF2 VDD2 VDD1 VP1 CPRF1
VCC
100pF 18
VCO190-1750T 100pF 18
18
ADF4208
100pF RF2IN
MUXOUT RF1IN
LOCK DETECT
100pF 51
AGNDRF1
51 30pF 30pF 10MHz 18k
OSCIN OSCOUT
DGNDRF1
DGNDRF2 AGNDRF2
DECOUPLING CAPACITORS (22 F/10pF) ON VDD, VP OF THE ADF4208, AND ON VCC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 8. Local Oscillator for WCDMA Receiver Using the ADF4208
-18-
SPI-COMPATIBLE SERIAL BUS
CLK DATA LE
REV. 0
ADF4206/ADF4207/ADF4208
INTERFACING ADSP-2181 Interface
The ADF4206/ADF4207/ADF4208 family has a simple SPIcompatible serial interface for writing to the device. SCLK, SDATA, and LE (Latch Enable) control the data transfer. When LE goes high, the 22 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Latch Truth Table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 ms. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 10 shows the interface between the ADF420x family and the ADSP-21xx Digital Signal Processor. As previously noted, the ADF420x family needs a 22-bit serial word for each latch write. The easiest way to accomplish this using the ADSP21-xx family is to use the Autobuffered Transmit Mode of operation with Alternate Framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 22-bit word. To program each 22-bit latch, store the three 8-bit bytes, enable the Autobuffered mode and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
Figure 10 shows the interface between the ADF420x family and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF420x family needs a 22-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. On first applying power to the ADF420x family, it requires four writes (one each to the R counter latch and the AB counter latch for both RF1 and RF2 side) for the output to become active. When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be about 180 kHz.
SCLOCK DT
SCLK SDATA LE
ADSP-21xx
TFS
ADF4206/ ADF4207/ ADF4208
I/O FLAG
MUXOUT (LOCK DETECT)
Figure 10. ADSP-21xx to ADF420x Family Interface
SCLOCK MOSI
SCLK SDATA LE
ADuC812
I/O PORTS
ADF4206/ ADF4207/ ADF4208
MUXOUT (LOCK DETECT)
Figure 9. ADuC812 to ADF420x Family Interface
REV. 0
-19-
ADF4206/ADF4207/ADF4208
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Thin Shrink Small Outline Package (TSSOP) (RU-16)
0.201 (5.10) 0.193 (4.90)
Thin Shrink Small Outline Package (TSSOP) (RU-20)
0.260 (6.60) 0.252 (6.40)
16
9
20
11
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 8
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 10
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
-20-
REV. 0
PRINTED IN U.S.A.
C01036-2.5-3/01 (0)

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